In order to develop long-lived and robust power conductor modules, especially the upper and lower connections of the semiconductor (upper side and lower side) have high thermal and electrical requirements. Usually, the lower side of the semiconductor is connected by a soldered connection or partly also by a sintered or diffusion soldered connection.
Normally, the upper side of the semiconductor comprises a metallisation or a metal layer that is optimised for the bonding process of thick aluminium wires. In spite of such highly deformable metallisation layers on the upper and lower side of the semiconductor, the semiconductors continue to become thinner in order to reduce the electrical losses. Currently, power semiconductors on the market have a total thickness of 70 μm. Research institutes have already presented the first wafers with the extreme thickness of only 10 μm.
The upper side chip connection has a vary large influence on the limitation of the life duration of a power module. A very robust sintered connection on the lower side of a chip only causes a slight increase in the module life duration, as the failure of the aluminium wires on the upper side of the semiconductor is the limiting factor.
For many years, the Al-bonding has been an established technology in the production lines for power electronics. A continuous optimisation of the bonding processes has caused an increase in the expected life duration of this connection. However, this high level is approximately at the physical limit of the stressability of an aluminium weld connection, so that large steps in the life duration expectation can only be realised by new concepts in the design and bonding technique. This requirement is also supported by the fact that already now the sintering technology (compared with the soldering technology) on the lower side of the semiconductor contributes to a two-figure increase in the factor of the life duration expectation.
Further, during the process difficulties occur in the handling of the 70 μm thin semiconductors (and those difficulties are expected to increase heavily with even thinner semiconductors!) Thus, both for the parameterisation of the production and test processes and for the configuration of the concepts, the very thin silicon layer is an increasing profit risk in the production. The risk of fracture exists not only due to thermo mechanical stress, but also due to light loads during the production processes (for example mounting of the contact needle for high current tests at wafer level).